(1) Field of the Invention
The present invention relates to semiconductor devices including, for example, resistors and methods for fabricating the same.
(2) Disclosure of Related Art
With recent development of information communication equipment, semiconductor devices such as system large scale integration (LSI) are required to have high processing ability. To meet this requirement, transistors have been designed to operate at higher speed. In particular, complementary field-effect transistors (FETs) composed of n-channel metal oxide semiconductor (NMOS) and p-channel metal oxide semiconductor (PMOS) transistors are widely used because of their low power consumption. Increase in speed of the complementary FETs has been achieved mainly by downsizing the structures thereof and is supported by development of lithography for processing semiconductor elements. However, in recent years, the required minimum processing dimensions come to be equal to or smaller than the wavelength level of light used in lithography. Therefore, further miniaturization becomes more difficult.
In view of this, techniques for enhancing the device performance of transistors without the need for size reduction are demanded. One of the techniques is a strained silicon technique for changing carrier mobility by deforming the crystal structure of silicon. Transistors employing the strained silicon technique may have larger carrier mobility than transistors made of bulk silicon, and thus NMOS and PMOS transistors are allowed to have higher current driving abilities. Therefore, for devices employing the strained silicon technique, device performance is enhanced without reduction of device size.
As such a technique for forming strained silicon, a stress memorization technique (SMT) is proposed in, for example, K. Ota et al., IEDM 2002, p 27. Specifically, in the SMT, an isolation region, a gate insulating film and a gate electrode are formed in/on a semiconductor substrate, and then ion implantation is performed on an extension region and source/drain regions. Thereafter, an SMT film is deposited over the semiconductor substrate and is subjected to annealing, thereby causing stress from the SMT film to be memorized in a channel region. As the SMT film, a laminated film in which an underlying film made of a silicon oxide film and a stressor film made of a silicon nitride film and having tensile stress are stacked in this order is generally used. Though this SMT film is removed after the annealing, the stress memorized in the channel region remains after the removal of the SMT film. Accordingly, in an NMOS transistor, mobility of electrons increases so that the current driving ability is enhanced.
Complementary metal oxide semiconductor (CMOS) transistors are composed of NMOS transistors and PMOS transistors and it is desirable that both types of transistors have high current driving abilities. However, as reported in, for example, C. Ortolland et al., VLSI 2006, pp.96-97, the use of an SMT causes the current driving ability to deteriorate for PMOS transistors. This document shows the reason for deterioration of current driving ability of a PMOS transistor is that annealing performed with the PMOS transistor covered with an SMT film causes the activation rate of boron (B) as a p-type impurity to decrease. Specifically, when the transistor is covered with a silicon nitride film serving as a stressor film, hydrogen in a silicon oxide film serving as an underlying film is not diffused toward the outside of a semiconductor substrate during annealing. This seems to result in a decrease in activation rate of boron (B) contained in the semiconductor substrate. In view of this, to prevent deterioration of current driving ability of the PMOS transistor, the process of removing the silicon nitride film on the PSMOS transistor and then performing annealing with only the NMOS transistor covered with the SMT film is effective.